The present invention relates to multi-chip package memory semiconductor devices and more particularly to a semiconductor device including a DRAM and a non-volatile memory integrally.
A list of references cited in this specification is as follows and reference numbers will be used to represent the references. “Ref. 1 ” LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet (retrieved on Apr. 21, 2000, Internet <URL:http://www.sharpsma.com/index.html>); “Ref. 2 ” EPO566306A2 (laid open on Oct. 20, 1993); “Ref. 3 ” JP-A-8-305680 (laid open on Nov. 22, 1996); “Ref. 4 ” JP-A-11-204721 (laid open on Jul. 30, 1999); and “Ref. 5 ” JP-A-10-11348 (laid open on Jan. 16, 1998).
Disclosed in “Ref. 1 ” is a multi-chip package semiconductor memory in which a flash memory (32M-bit capacity) and an SRAM (4M-bit capacity) that are in the form of a stacked chip are integrally molded in a FBGA type package. The flash memory and SRAM have each an address input terminal and a data input/output terminal that are shared by an input/output electrode of the FBGA type package. But their control terminals are independent of each other.
Illustrated in FIG. 17 of “Ref. 2 ” is a multi-chip package semiconductor memory having a flash memory chip and a DRAM chip that are integrally molded in a lead frame type package. Further, illustrated in FIG. 1 is a memory in which a flash memory and a DRAM have each an address input terminal, a data input/output terminal and a control terminal that are shared by an input/output electrode of the package to assure input/output operation.
Described in “Ref. 3” is a semiconductor device in which an SRAM chip is mounted on a die pad, a flash memory and a microprocessor chip that are connected to each other through bump electrodes are mounted on the SRAM chip, and these chips are integrally molded in a package of lead terminal type.
Illustrated in FIG. 15 of “Ref. 4” is a semiconductor device in which two smaller chips are mounted on the back of a single larger chip through an insulating plate and a resulting structure is integrally molded in a lead frame type package. There is a description that a chip combination of a flash memory chip, a DRAM chip and an ASIC (Application Specific IC) is mountable to permit an LSI mounted with a memory logic to be realized with a single package.
Described in “Ref. 5” is a technology in which two DRAM blocks are provided to store the same data in duplication and the timing of refresh is shifted between the two DRAM's to avoid a collision between external access and refresh of the DRAM. This control operation is carried out with a DRAM controller, which DRAM controller issues physically independent address signals and control signals to the two DRAM blocks.
Before making this invention, the present inventors have studied a cellular phone and a memory module for use therein having a flash memory and an SRAM that are mounted in a single package. The flash memory accommodates, in addition to an OS (operating system) of a cellular phone system, programs of communication and applications. On the other hand, the SRAM stores telephone numbers, an address book and terminating sounds and the like and besides, it maintains a work area temporarily used during execution of applications.
To hold data to be stored such as the telephone numbers and address book, a power source for holding data is connected to the SRAM even when a power source of the cellular phone remains to be turned off. For the purpose of holding the data for a long period, data hold current in the SRAM is desired to be small. However, the work area used by applications grows as the kinds of functions to be added to the cellular phone (such as distribution of music and games) increase and expectantly, there is a need for an SRAM of larger memory capacity. Further, up-to-date cellular phones become drastically highly functional and it has been found that with time, even an SRAM of increased capacity will have difficulties in coping with the highly graded function. More particularly, increasing the SRAM capacity encounters problems as below. In an SRAM of large capacity, the data hold current increases by an increment of storage capacity and in addition, an increased gate leakage current causes the data hold current to increase. This is because when the oxide insulating film of a MOS transistor is made to be thin by introducing a fine working process for the purpose of realizing a large-capacity SRAM, tunnel current flows from the gate to the substrate and as a result the data hold current increases.